Memory devices, HEMTs and FinFETs are key components in today's semiconductor industry. Improving the characteristics of these devices is critical to enhance their performance. One of the issues of memory cells is the relatively high read and write voltages needed to program and erase the cell. This issue becomes more critical if a high-k dielectric were used in the gate charge trapping structure. These relatively large voltages are required so that the charges in the channel can overcome the dielectric barrier and tunnel into the charge trapping region under the gate and vise versa. Moreover, in FinFETs, HEMTs and Tri-gate transistors, for example, scaling down the transistor dimensions may decrease the gate control over the channel. Implementation of this invention may provide faster read and write speeds and lower read and write voltages for memory cells. It may also provide a better gate control over the channel in FinFETs, HEMTs and Tri-gate transistors